The present invention relates to a test system and, in particular, to a test system which can be calibrated to take account of propagation delays which occur in signal paths leading to respective pins of the test system.
Test systems are widely used to enable circuit components such as boards or individual electronic components to be tested. The known test systems generally comprise sophisticated test electronics including signal generation circuits for producing a large number of test signals including D.C. voltage levels and timing signals. It may be necessary to provide the capacity to generate several thousand different test signals and thus the test electronics are expensive and must be adaptable so they can be used to test a variety of different components. Thus, it is conventional practice to provide an interface known as a test "fixture" to connect a board or other component to be tested to the test electronics.
Typically, the test electronics is housed in a cabinet provided with an array of output pins housed in a structure known as a "receiver". When a new design of board is to be tested, a fixture is produced which acts as an interface between the board under test and the receiver. The fixture effectively plugs into the receiver and the board under test plugs into the fixture. Signal paths are wired between fixture pins that contact the receiver and fixture pins that contact the board.
In many test operations, it is necessary to generate timing signals that arrive at the board with a predetermined phase relationship. Although the appropriate phase relationship can be established at the source of the signals in the signal generator, these signals are propagated along different signal paths to the receiver, and along different signal paths through the fixture. The different signal paths introduce propagation delays which may vary from one path to another.
The problem of non-uniform propagation delays is well known and is conventionally addressed by incorporating calibration circuitry. Such circuitry includes delay devices arranged in the signal paths to add delays selectively such that all of the propagation delays in the signal paths are substantially equal. Various proposals have been made to connect propagation delay measurement circuits either to the receiver (on the assumption that propagation delays in the fixture have been approximately equalized by careful design of the signal paths within the fixture) or to pins that contact the component under test directly.
One known system is described in the article "Closed loop error correction: a unique approach to test system calibration" by Mark Dahl, published as paper 32.2 of the 1987 International Test Conference, CH 2347-2/87/0000/0772. This paper describes calibration support circuitry which is a separate unit from the test system and can, therefore, be placed in a mobile calibration unit such that can be shared by many tester systems. Contacts of a test fixture are probed by a signal probe that is driven by an X-Y positioning device across the fixture. The positioner moves at a speed that enables, for example, 256 pin channels to be probed in less than 60 seconds. The source of signals picked up by the probe are identified by reference to the location of the positioner relative to the fixture. This arrangement avoids the conventional requirement for each tester to incorporate internal calibration circuitry to which signals are routed back from the fixture pins through a complex network of cables and switches, but this is at the expense of providing a precision piece of equipment to drive the positioner, and using a standard fixture structure that fits the positioning equipment.
It is also known to provide a simple electrical continuity detector in the form of a probe that is manually "wiped" across the pins of, for example, a fixture. Signals picked up by the probe enable the presence or absence of DC levels on the fixture pins to be detected. This system does not enable information to be derived from the wiped pins which could be used, for example, to measure propagation delays in signal paths leading to the pins.
It is an object of the present invention to provide a test system which can be used to derive timing calibration data using a simple probe to wipe pins carrying timing signals.
According to the present invention, there is provided a test system for determining propagation delays in signal paths leading to respective pins in an array of pins, comprising means for applying timing signals to each of the signal paths in parallel, means for applying pin identifying signal to each of the signal paths, a different pin identifying signal being applied to each signal path, a probe which can be wiped across the pins to detect signals on each pin with which it comes into contact, means for identifying a pin with which the probe is in contact from the pin identifying signals detected by the probe, and means for calculating the propagation delay in the signal path leading to an identified pin with which the probe is in contact from the timing signals detected by the probe.
Preferably, the timing signals and pin identifying signals are applied alternately to each of the signal paths. Each pin identifying signal may comprise a rectangular wave embodying a digital code allocated to the respective pin, and means may be provided to generate a strobe pulse signal synchronized with the pin identifying signals applied to the signal paths such that each strobe pulse coincides in time with a respective portion of the rectangular wave that represents one bit of the digital code. The duration of each portion of the rectangular wave is selected to be sufficient to ensure that the strobe pulses continue to coincide in time with the respective portions of the rectangular wave despite delays in propagation of the rectangular waves in the signal paths leading to the pins for which they are detected, and means are provided to sample the identifying signals in synchronism with the strobe pulses to derive the digital codes.
Preferably, the timing signals comprise a rectangular wave of fixed frequency applied in phase to each signal path, and the calculating means comprises means for comparing the phase of the timing signals detected by the probe. The calculating means may comprise means for sampling each timing signal detected by the prober with a common clock signal having a different frequency from said fixed frequency to produce sampled data. The calculating means may further comprise means for detecting an edge in the sampled data, and means for recording a cycle count corresponding to the number of cycles in the common clock signal from the initiation of a timing signal to the detection of an edge.
Preferably, means are provided for detecting loss of electrical contact between the probe and a pin in an interval of time during which identifying or timing signals are being applied to that pin, signals detected during intervals of time in which loss of electrical contact is detected being rejected.
Preferably, each identifying signal and timing signal comprises a rectangular waveform which alternates between two voltage levels, and means are provided to maintain the probe at a third voltage level to the probe if the probe is not in electrical contact with any external voltage source, the loss of contact detecting means comprising means for detecting the said third voltage.
The invention also provides a method for determining propagation delays in signal paths leading to respective pins in an array of pins, wherein timing signals are applied to each of the signal paths in parallel, pin identifying signals are applied to each of the signal paths such that each signal path and the pin to which it is connected receives a different pin identifying signal, a probe is wiped across the pins to detect signals on each of the pins with which it comes into contact, any pin with which the probe is in contact is identified by detection of the pin identifying signal, timing signals on an identified pin are detected, and the propagation delay in the signal paths to the identified pin is calculated from the detected timing signals.